In various digital circuits, flip-flops are the fundamental sequential logic element. Power dissipated or consumed in the flip-flops makes up a significant portion of the total power dissipation in a circuit design. Thus, by reducing power dissipation in the flip-flops, the performance of the design can be improved drastically. Also, in digital designs, comprising millions of flip-flops and clock tree buffers, there is a high amount of switching current during dynamic transitions. The current in clock tree buffers cannot be controlled, but we can lower the switching current in the flip-flops to lower the electromagnetic emissions.
FIG. 1 illustrates a conventional flip-flop circuit 100. The flip-flop circuit 100 includes a master latch 102, a slave latch 104, a clock buffer 106, an inverter 108, transmission gates 110 and 112 and inverters 114 and 116. The master latch 102 includes a tri-state inverter 118 and an inverter 120. The slave latch 104 includes a tri-state inverter 122 and an inverter 124. The tri-state inverters 118 and 122 include a pair of PMOS transistors and a pair of NMOS transistors. The connection of the master latch 102 and the slave latch 104 is as shown in FIG. 1. The clock buffer 106 includes a pair of inverters 126 and 128. The transmission gates 110 and 112 include an NMOS transistor and a PMOS transistor.
When the clock is low, the master latch 102 becomes transparent, i.e., the transmission gate 110 at an input D turns ON to transfer data D. The slave latch 104 restores the previous flip-flop output by enabling the tri-state inverter 122 in the feedback path and the rest of the circuit is inactive. When the clock is high, the slave latch 104 becomes transparent through the transmission gate 112. The data at the output of inverter 120 gets transferred to an output Q through the transmission gate 112, and the inverters 124 and 114. The data gets transferred to an output QN through the transmission gate 112 and the inverter 116. In the master latch 102, the feedback tri-state inverter 118 is ON, restoring the previous data. The clock buffer circuit 106 includes two inverters 126 and 128 whose output gives two 180 degree shifted clocks on which the master latch 102 and the slave latch 104 operate. The inverter 126 is mainly introduced to achieve clock slope independency; such that on different clock cycles the flip-flop slope characteristics do not change much.
The flip-flop operation can be divided into three states. State I—clock constant data toggle, state II—data constant clock toggle and state III—clock change flip-flop output (Q) change. In state I, depending on the clock state (high or low), the power dissipation is less or more (respectively) and is governed by data switching only. When in the data constant clock toggle state, i.e., state II, due to clock switching (on the order of MHz), a lot of power gets dissipated in the clock buffer circuit 106 as well as in the master latch 102 and in the slave latch 104. In state III, the clock flip-flop output Q changes state, there is power dissipation that cannot be avoided. Data activity in most digital designs is small compared to the clock activity. Therefore, it is desired to reduce the power dissipation in the case of data constant clock toggling (i.e., state II). Already some work has been done in this field in order to reduce the power dissipation.
FIG. 2 illustrates a conventional low power flip-flop circuit 200, which reduces power dissipation in a State II mode. The circuit 200 comprises the conventional flip-flop circuit 100 as illustrated in FIG. 1 and an internal clock generating circuit 206. The clock generating circuit 206 comprises a transmission gate 226, multiple inverters such as 228, 230, 232 and a sensing circuit, which is a two input XOR gate 236 and a NOR gate 234.
The flip-flop output Q and the data input D is fed to the XOR gate 236. The output of the XOR gate 236 is connected to an input of the NOR gate 234. The NOR gate 234 has its other input connected to a signal CPN and the output is a control signal S. The control signals S and SN control the transfer of an external clock CLK to an internal clock CP through the transmission gate 226. The output of the transmission gate 226 is supplied to two back-to-back connected inverters 228 and 230. The inverters 228 and 230 hold the clock value when the transmission gate 226 is disabled and also provide two phase clock signals CPN and CP upon which the flip-flop operates.
FIG. 4 illustrates the functionality of the flip-flop circuit 200. When D and Q are same, S is low and when D and Q are different, S is high. When S is high the transmission gate 226 is ON and the clock signal is passed to a node CP. When S is low, the transmission gate 226 is OFF and the previous value at the transmission gate 226 is restored at the node CP. However, when S is high, the transmission gate 226 is ON and the CLK signal makes a transition from 0 to 1. Then, at the node CP, the inverter 228 opposes the transition. The inverter 228 tries to drive the node CP to 0, whereas, through the transmission gate 226, the CLK tries to drive it to 1, resulting in a contention at the node CP. This results in high power dissipation and an imperfect rise at the node CP.
FIG. 6 illustrates the internal clock signals of flip-flop circuits 200 and 300. For the flip-flop circuit 200, the internally generated clock signal CP has a very poor rise. First, the clock rises to an intermediate voltage value sharply, stays there for some time, and then rises to a value VDD. Since the CP signal drives the master and slave of the flip-flop circuit, the poor nature of the signal degrades the delay, the setup time, the hold time, and the power dissipation associated with the flip-flop circuit. The structure is very sensitive to input clock slope. With an increase in input clock slope, the rise time of the internal CP signal also increases, and, it stays at intermediate value for extra time resulting in higher power dissipation, delay, and setup-hold. There is also a risk of functionality failure in this structure. If in manufacturing, due to a slight variation in doping levels, the NMOS becomes faster than the PMOS, the node CP may not be able to rise due to the inverter 228 NMOS pulling the node CP down to 0. As a result, the internal CP signal will always remain at 0 and no external data will be latched. The sizing of transistors is very critical in the above flip-flop, as the transmission gate 226 has to be made very strong to drive the node CP, and the inverter 228 has to be made weak. The area of the flip-flop also increases, to make the transistor strong, and its gate width should also be increased. In order to weaken the transistor, its gate length should be increased. Hence, the flip-flop circuit 200 is not suitable, especially for ultra deep sub-micrometer (DSM) technologies, where mismatches because of the technology are high.
Therefore, there is a need for a novel flip-flop circuit capable of providing low power for low electromagnetic interference (EMI) applications.